With the reduced sizes and improved functions of information communication apparatuses and office electronic apparatuses, semiconductor devices (semiconductor integrated circuit devices: hereinafter referred to as semiconductor chips) mounted in these electronic apparatuses have been desired to have a smaller size as well as an increased number of external terminals for input and output.
Thus, with a conventional configuration in which a peripheral portion of the semiconductor chip is used as an area exclusively occupied by electrode portions (electrode pads) for connection to external circuits, it has been difficult to achieve both an increase in the number of external terminals and a size reduction. Thus, a technique called pad on element and a flip chip technique have more often been adopted; the pad on element forms electrode pads also on an active area, and the flip chip technique forms projecting electrodes called bumps on the electrode pads and connects the semiconductor chips to external circuits through the bumps.
On the other hand, significantly improved semiconductor manufacturing processes have contributed to further miniaturizing the structure of the semiconductor chip while further increasing integration degree. Copper wiring, having a relatively low resistance, has often been used as a wiring material. What is called a low-k material, having a small dielectric constant, has often been used as an interlayer insulating film.
Furthermore, the recently increased integration degree has led to complication of various semiconductor manufacturing processes. Whether or not semiconductor elements on each semiconductor chip normally operate depends on a variation in conditions for the manufacturing processes or the like. Thus, the properties of the semiconductor elements or various process values obtained during the semiconductor manufacturing process are inspected in a wafer state to estimate whether or not the semiconductor chip is acceptable and to determine whether or not the semiconductor manufacturing process normally operates.
For example, electrical property inspections are carried out to contact probes with electrode pads formed in each semiconductor chip area so as to be electrically connected to a plurality of semiconductor elements in the area. Furthermore, semiconductor elements (monitor elements) of a basic configuration and electrode pads electrically connected to the semiconductor element are arranged on a scribe area. The monitor elements are then inspected to estimate whether or not the properties of integrated circuit in the semiconductor chip area is acceptable. Even if the manufacturing process is abnormal, the abnormality is found early and fed back to minimize the occurrence probability of defective process articles.
However, a problem with miniaturized and highly integrated semiconductor chips is a shock that may result from wire bonding or inner lead bonding on the electrode pads or from contacting the probes with the electrode pads during electronic property inspections. Particularly when the electrode pads are formed on the active area or the low-k material is used as an interlayer insulating film, the shock often damages not only the electrode pads but also the interlayer insulating film, a wiring layer, and active elements, all of which are arranged under the electrode pads. This may degrade the electrical properties.
To avoid this, for example, Japanese Patent No. 3398609 proposes a technique of forming hard projecting electrodes of Ni-containing metal on the electrode pads so as to allow the projecting electrodes to act against the shock resulting from the wire bonding or inner lead bonding, thus inhibiting possible damage to the semiconductor elements.
Moreover, with the conventional method, when the flip chip scheme is used to connect the semiconductor chip to an external circuit, the bumps (projecting electrodes) on the electrode pads are pressure-welded and connected to the external circuit using an anisotropic conductive sheet (ACF). However, a method of forming bumps of solder and melting the bumps for connection has been proposed and gathering much attention because of the method's high possibility of being able to inhibit possible damage to the semiconductor elements.
However, the melting of the solder bumps for connection enables a reduction in damage during mounting but cannot avoid damage during the electrical property inspections. When the electrical property inspections are carried out on the electrode pads with no solder bumps formed thereon yet, the interlayer insulating film may be cracked or the electrical properties may be affected as described above. When the electrical property inspections are carried out after the formation of the solder bumps, the contact of the inspection probes may deform the solder bumps, affecting the mounting.
Thus, when the solder bumps are to be formed by a printing method or a ball mounting method, it is possible to form UBM (Under Bump Metal) of Ni or Au on the electrode pads before forming the solder bumps and to contact the inspection probe with the UBM for the electrical property inspections. This method enables electric connections to be ensured even with a 10ad on the inspection probe set at a small value This enables the inhibition of possible damage to the underlying structure of the electrode pads.
Methods of forming the projecting electrode are roughly classified into two types. One of the types utilizes electroplating. That is, a metal thin film is formed all over the surface of the wafer by sputtering or the like. An insulating film called plating resist is formed which has openings at positions where the projecting electrodes are to be provided. The plating resist is then grown into metal projections at the openings in the plating resist by electroplating. The metal projections are then used as a mask to etch away unwanted parts of the metal thin film to form projecting electrodes. However, this method uses the complicated manufacturing process, sharply increasing costs.
The other type is a method utilizing electroless plating. For example, an Al layer is formed all over the surface of the wafer at predetermined positions. An insulating film is then formed which has openings at predetermined electrode positions. The Al in a surface of the Al layer (this corresponds to the electrode pad) exposed from the openings is replaced with Zn by zincating. The wafer is subsequently immersed in an electroless plating solution to substitute Ni for Zn to form Ni projecting electrodes. An Au film is further formed on the surface of each of the Ni projecting electrodes. This method immerses the wafer in the electroless plating solution to selectively grow plating on the metal exposed portions, enabling the projecting electrodes to be formed. This eliminates the need for a photolithography process using a mask, allowing a reduction in manufacturing costs. This method is also used to form the projecting electrodes and UBM in Japanese Patent No. 3398609.
However, the formation of the projecting electrodes utilizing electroless plating also poses a problem. When the monitor elements and the electrode pads therefor are formed in the scribe area, the projecting electrodes are also formed on the electrode pads by electroless plating. Consequently, during a dicing step in which the semiconductor wafer is divided into individual semiconductor chips, significant chipping may occur or the wiring layer or interlayer insulting film under the projecting electrodes may be cracked. This may also affect the semiconductor chips.
The problem is more significant in highly miniaturized and integrated semiconductor wafers; the occurrence probability of chipping and cracking further increases. A semiconductor wafer of this kind uses the wiring layer mainly comprising Cu or the low-k material as an interlayer insulating film as described above. Thus, if not only the electrode pads but also the projecting electrodes are formed in the scribe area, the wafer is diced at the area in which the very hard projecting electrodes and the fragile low-k film are mixed. This is likely to increase the occurrence probability of chipping and to cause burrs at the electrode pads.